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LH532048 FEATURES * 131,072 words x 16 bit organization * Access time: 100 ns (MAX.) * Static operation * TTL compatible I/O * Three-state outputs * Single +5 V power supply * Power consumption: Operating: 412.5 mW (MAX.) Standby: 550 W (MAX.) * Packages: 40-pin, 600-mil DIP 40-pin, 525-mil SOP 44-pin, 650-mil QFJ (PLCC) DESCRIPTION The LH532048 is a 2M-bit mask-programmable ROM organized as 131,072 x 16 bits. It is fabricated using silicon-gate CMOS process technology. 40-PIN DIP 40-PIN SOP CMOS 2M (128K x 16) MROM PIN CONNECTIONS TOP VIEW NC CE D15 D14 D13 D12 D11 D10 D9 D8 GND D7 D6 D5 D4 D3 D2 D1 D0 OE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC NC A16 A15 A14 A13 A12 A11 A10 A9 GND A8 A7 A6 A5 A4 A3 A2 A1 A0 532048-1 Figure 1. Pin Connections for DIP and SOP Packages 44-PIN PLCC VCC D13 D14 D15 A16 A15 A14 NC NC NC CE TOP VIEW 6 D12 D11 D10 D9 D8 GND NC D7 D6 D5 D4 7 8 9 10 11 12 13 14 15 16 17 5 4 3 2 1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 A13 A12 A11 A10 A9 GND NC A8 A7 A6 A5 18 19 20 21 22 23 24 25 26 27 28 D3 D2 D1 D0 A0 A1 A2 A3 OE NC A4 532048-2 Figure 2. Pin Connections for QFJ (PLCC) Package 1 LH532048 CMOS 2M MROM A16 38 A15 37 A14 36 A13 35 A12 34 3 D15 MEMORY MATRIX (131,072 x 16) 4 D14 5 D13 6 D12 7 D11 8 D10 OUTPUT BUFFER A9 A8 A7 A6 31 29 28 27 ADDRESS BUFFER A11 33 A10 32 ADDRESS DECODER 9 D9 10 D8 12 D7 13 D6 14 D5 15 D4 16 D3 17 D2 18 D1 A5 26 A4 25 A3 24 A2 23 A1 22 A0 21 COLUMN SELECTOR CE 2 CE BUFFER TIMING GENERATOR SENSE AMPLIFIER 19 D0 OE 20 OE BUFFER 40 VCC NOTE: Pin numbers apply to the 40-pin DIP or SOP. 11 30 GND 532048-3 Figure 3. LH532048 Block Diagram PIN DESCRIPTION SIGNAL PIN NAME SIGNAL PIN NAME A0 - A16 D0 - D15 CE OE Address input Data output Chip enable input Output enable input VCC GND NC Power supply (+5 V) Ground No connection 2 CMOS 2M MROM LH532048 A16 42 A15 41 A14 40 A13 39 A12 38 4 D15 MEMORY MATRIX (131,072 x 16) 5 D14 6 D13 7 D12 8 D11 9 D10 OUTPUT BUFFER A9 A8 A7 A6 35 32 31 30 ADDRESS BUFFER A11 37 A10 36 ADDRESS DECODER 10 D9 11 D8 14 D7 15 D6 16 D5 17 D4 18 D3 19 D2 20 D1 A5 29 A4 28 A3 27 A2 26 A1 25 A0 24 COLUMN SELECTOR CE 3 CE BUFFER TIMING GENERATOR SENSE AMPLIFIER 21 D0 OE 22 OE BUFFER 44 VCC NOTE: Pin numbers apply to the 44-pin QFJ. 12 34 GND 532048-4 Figure 4. LH532048 Block Diagram 3 LH532048 CMOS 2M MROM TRUTH TABLE CE OE DATA OUTPUT SUPPLY CURRENT H L L X H L High-Z High-Z D0 - D15 Standby Operating Operating NOTE: X = H or L, High-Z = High-impedance ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING UNIT Supply voltage Input voltage Output voltage Operating temperature Storage temperature VCC VIN VOUT Topr Tstg - 0.3 to +7.0 - 0.3 to V CC + 0.3 - 0.3 to V CC + 0.3 0 to +70 -65 to +150 V V V C C RECOMMENDED OPERATING CONDITIONS (TA = 0C to +70C) PARAMETER SYMBOL MIN. TYP. MAX. UNIT Supply voltage VCC 4.5 5.0 5.5 V DC CHARACTERISTICS (VCC = 5 V 10%, TA = 0C to +70C) PARAMETER SYMBOL CONDITIONS MIN. MAX. UNIT NOTE Input `High' voltage Input `Low' voltage Output `High' voltage Output `Low' voltage Input leakage current Output leakage current VIH VIL VOH VOL | ILl | | ILO | ICC1 ICC2 ICC3 ICC4 IOH = - 400 A IOL = 2.0 mA V IN = 0 V to VCC V OUT = 0 V to VCC tRC = 100 ns tRC = 1 s tRC = 100 ns tRC = 1 s CE = V IH CE = V CC - 0.2 V f = 1 MHz TA = 25C 2.2 - 0.3 2.4 VCC + 0.3 0.8 V V V 0.4 10 10 75 65 70 60 3 100 10 10 V A A mA mA mA mA mA A pF pF 1 2 2 3 3 Operating current Standby current Input capacitance Output capacitance ISB1 ISB2 CIN COUT NOTES: 1. CE/OE = VIH 2. VIN = VIH or VIL, CE = VIL, outputs open 3. VIN = (VCC - 0.2 V) or 0.2 V, CE = 0.2 V, outputs open 4 CMOS 2M MROM LH532048 AC CHARACTERISTICS (VCC = 5 V 10%, TA = 0C to +70C) PARAMETER SYMBOL MIN. MAX. UNIT NOTE Read cycle time Address access time Chip enable access time Output enable delay time Output hold time CE to output in High-Z OE to output in High-Z tRC tAA tACE tOE tOH tCHZ tOHZ 100 100 100 55 0 50 ns ns ns ns ns ns ns 1 NOTE: 1. This is the time required for the outputs to become high-impedance. AC TEST CONDITIONS PARAMETER RATING Input voltage amplitude Input rise/fall time Input/output reference level Output load condition 0.4 V to 2.6 V 10 ns 1.5 V 1 TTL + 100 pF CAUTION To stabilize the power supply, it is recommended that a high-frequency bypass capacitor be connected between the VCC pin and the GND pin. tRC A0 - A16 tAA (NOTE) CE tACE (NOTE) OE tOE (NOTE) tOHZ tOH tCHZ D0 - D15 NOTE: The output data becomes valid when the last intervals, tAA, tACE, or tOE, have concluded. DATA VALID 532048-5 Figure 5. Timing Diagram 5 LH532048 CMOS 2M MROM PACKAGE DIAGRAMS 40DIP (DIP040-P-0600) 40 21 DETAIL 13.45 [0.530] 12.95 [0.510] 1 52.30 [2.059] 51.70 [2.035] 20 0 TO 15 0.30 [0.012] 0.20 [0.008] 4.55 [0.179] 3.95 [0.156] 5.40 [0.213] 4.80 [0.189] 3.55 [0.140] 2.95 [0.116] 2.54 [0.100] TYP. 0.51 [0.020] MIN. 0.60 [0.024] 0.40 [0.016] MAXIMUM LIMIT MINIMUM LIMIT 15.24 [0.600] TYP. DIMENSIONS IN MM [INCHES] 40DIP 40-pin, 600-mil DIP 40SOP (SOP040-P-0525) 1.27 [0.050] TYP. 1.40 [0.055] 21 0.50 [0.020] 0.30 [0.012] 40 11.50 [0.453] 11.10 [0.437] 14.50 [0.571] 13.70 [0.539] 12.50 [0.492] 1 26.50 [1.043] 26.10 [1.028] 20 1.40 [0.055] 0.20 [0.008] 0.10 [0.004] 0.15 [0.006] 1.275 [0.050] 2.90 [0.114] 2.50 [0.098] 0.20 [0.008] 0.00 [0.000] 1.275 [0.050] MAXIMUM LIMIT MINIMUM LIMIT DIMENSIONS IN MM [INCHES] 40SOP 40-pin, 525-mil SOP 6 CMOS 2M MROM LH532048 44QFJ (QFJ044-P-0650) 1.27 [0.050] TYP. C1.1 5 1 40 10 35 16.60 [0.654] 17.60 [0.693] 17.40 [0.685] 16.00 [0.630] 15.20 [0.598] 15 30 0.56 [0.022] 0.36 [0.014] 20 16.60 [0.654] 17.60 [0.693] 17.40 [0.685] 25 0.85 [0.033] 1.80 [0.071] 0.25 [0.010] 4.60 [0.181] 4.20 [0.165] 2.35 [0.093] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 44QFJ-2 44-pin, 650-mil QFJ (PLCC) ORDERING INFORMATION LH532048 Device Type X Package D 40-pin, 600-mil DIP (DIP040-P-0600) N 40-pin, 525-mil SOP (SOP040-P-0525) U 44-pin, 650-mil QFJ (PLCC) (QFJ044-P-S650) CMOS 2M (128K x 16) Mask-Programmable ROM Example: LH532048D (CMOS 2M (128K x 16) Mask-Programmable ROM, 40-pin, 600-mil DIP) 532048-6 7 |
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